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Branches
Name | Last Modified | Last Commit |
---|---|---|
patch-hwe- |
2022-01-10 22:44:28 UTC |
crypto: hisilicon/qm - modify the uacce mode check
Author:
Kai Ye
crypto: hisilicon/qm - modify the uacce mode check As qm should register to uacce in UACCE_DEV_SVA mode, Signed-off-by: Kai Ye <yekai13@ |
hwe-5.13- |
2022-01-07 00:10:32 UTC |
crypto: hisilicon/qm - fix the uacce mmap failed
Author:
Kai Ye
crypto: hisilicon/qm - fix the uacce mmap failed Allocate an extra memory page for qp. This extra page is Signed-off-by: Kai Ye <yekai13@ |
hwe-5.13- |
2022-01-06 15:14:44 UTC |
PCI: Allow PASID on fake PCIe devices without TLP prefixes
Author:
zhangfei gao
PCI: Allow PASID on fake PCIe devices without TLP prefixes Some systems, e.g., HiSilicon KunPeng920 and KunPeng930, have devices that Add a pasid_no_tlp bit for this "PASID works without TLP prefixes" case and Set this bit for HiSilicon KunPeng920 and KunPeng930. [bhelgaas: squashed, commit log] |
hwe-5.11- |
2022-01-06 15:12:26 UTC |
PCI: Allow PASID on fake PCIe devices without TLP prefixes
Author:
zhangfei gao
PCI: Allow PASID on fake PCIe devices without TLP prefixes Some systems, e.g., HiSilicon KunPeng920 and KunPeng930, have devices that Add a pasid_no_tlp bit for this "PASID works without TLP prefixes" case and Set this bit for HiSilicon KunPeng920 and KunPeng930. [bhelgaas: squashed, commit log] |
hwe-5.11- |
2021-10-12 05:27:32 UTC |
(DROP ME) [DEBUGGING] kernel label for debugging
Author:
Taihsiang Ho
(DROP ME) [DEBUGGING] kernel label for debugging |
hwe-5.11- |
2021-07-13 19:48:48 UTC |
fixup
Author:
Taihsiang Ho
fixup |
hwe-5.11- |
2021-07-08 12:34:42 UTC |
tai: add debugging msg
Author:
Taihsiang Ho
tai: add debugging msg |
master- |
2020-04-01 13:48:41 UTC |
spi: HiSilicon v3xx: Use DMI quirk to set controller buswidth override bits
Author:
John Garry
spi: HiSilicon v3xx: Use DMI quirk to set controller buswidth override bits BugLink: https:/ The Huawei D06 board (and variants) can support Quad mode of operation. Since we have no current method in ACPI SPI bus device resource description Signed-off-by: John Garry <john.garry@ |
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