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Branches

Name Last Modified Last Commit
patch-hwe-5.13-next-lp1933301-crypto 2022-01-10 22:44:28 UTC
crypto: hisilicon/qm - modify the uacce mode check

Author: Kai Ye
Author Date: 2021-09-27 08:16:55 UTC

crypto: hisilicon/qm - modify the uacce mode check

As qm should register to uacce in UACCE_DEV_SVA mode,
this patch modifies to checks uacce mode before doing uacce
registration.

Signed-off-by: Kai Ye <yekai13@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

hwe-5.13-lp1933301-crypto-exp-01-effective-patch 2022-01-07 00:10:32 UTC
crypto: hisilicon/qm - fix the uacce mmap failed

Author: Kai Ye
Author Date: 2021-08-28 03:39:38 UTC

crypto: hisilicon/qm - fix the uacce mmap failed

Allocate an extra memory page for qp. This extra page is
used to set the device or qp status. But this page not
be used currently. Meanwhile it leads to dus size not equal
to mmap size as using uacce sva mode, and cause the app task
broken.

Signed-off-by: Kai Ye <yekai13@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

hwe-5.13-lp1933301-crypto-solution-01 2022-01-06 15:14:44 UTC
PCI: Allow PASID on fake PCIe devices without TLP prefixes

Author: zhangfei gao
Author Date: 2021-07-13 02:54:34 UTC

PCI: Allow PASID on fake PCIe devices without TLP prefixes

Some systems, e.g., HiSilicon KunPeng920 and KunPeng930, have devices that
appear as PCI but are actually on the AMBA bus. Some of these fake PCI
devices support a PASID-like feature and they do have a working PASID
capability even though they do not use the PCIe Transport Layer Protocol
and do not support TLP prefixes.

Add a pasid_no_tlp bit for this "PASID works without TLP prefixes" case and
update pci_enable_pasid() so it can enable PASID on these devices.

Set this bit for HiSilicon KunPeng920 and KunPeng930.

[bhelgaas: squashed, commit log]
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/1626144876-11352-2-git-send-email-zhangfei.gao@linaro.org
Link: https://lore.kernel.org/r/1626144876-11352-3-git-send-email-zhangfei.gao@linaro.org
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

hwe-5.11-lp1933301-crypto-solution-01 2022-01-06 15:12:26 UTC
PCI: Allow PASID on fake PCIe devices without TLP prefixes

Author: zhangfei gao
Author Date: 2021-07-13 02:54:34 UTC

PCI: Allow PASID on fake PCIe devices without TLP prefixes

Some systems, e.g., HiSilicon KunPeng920 and KunPeng930, have devices that
appear as PCI but are actually on the AMBA bus. Some of these fake PCI
devices support a PASID-like feature and they do have a working PASID
capability even though they do not use the PCIe Transport Layer Protocol
and do not support TLP prefixes.

Add a pasid_no_tlp bit for this "PASID works without TLP prefixes" case and
update pci_enable_pasid() so it can enable PASID on these devices.

Set this bit for HiSilicon KunPeng920 and KunPeng930.

[bhelgaas: squashed, commit log]
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/1626144876-11352-2-git-send-email-zhangfei.gao@linaro.org
Link: https://lore.kernel.org/r/1626144876-11352-3-git-send-email-zhangfei.gao@linaro.org
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

hwe-5.11-lp1933301-crypto-comment17 2021-10-12 05:27:32 UTC
(DROP ME) [DEBUGGING] kernel label for debugging

Author: Taihsiang Ho
Author Date: 2021-10-12 05:27:32 UTC

(DROP ME) [DEBUGGING] kernel label for debugging

hwe-5.11-rasdaemon-deb 2021-07-13 19:48:48 UTC
fixup

Author: Taihsiang Ho
Author Date: 2021-07-13 19:48:48 UTC

fixup

hwe-5.11-lp1933301-crypto 2021-07-08 12:34:42 UTC
tai: add debugging msg

Author: Taihsiang Ho
Author Date: 2021-07-08 11:39:46 UTC

tai: add debugging msg

master-next-lp1867588-patchset 2020-04-01 13:48:41 UTC
spi: HiSilicon v3xx: Use DMI quirk to set controller buswidth override bits

Author: John Garry
Author Date: 2020-02-28 15:18:51 UTC

spi: HiSilicon v3xx: Use DMI quirk to set controller buswidth override bits

BugLink: https://launchpad.net/bugs/1867588

The Huawei D06 board (and variants) can support Quad mode of operation.

Since we have no current method in ACPI SPI bus device resource description
to describe this information, use DMI to detect the board, and set the
controller buswidth override bits.

Signed-off-by: John Garry <john.garry@huawei.com>
Link: https://lore.kernel.org/r/1582903131-160033-4-git-send-email-john.garry@huawei.com
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 34e608b023e96f51b31274435b49c8ae61e2389f)
Signed-off-by: Taihsiang Ho (tai271828) <taihsiang.ho@canonical.com>

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