lp:~bladernr/ubuntu/+source/linux/+git/bionic

Author: Dave Hansen
Author Date: 2022-09-22 18:47:45 UTC

ACPI: processor idle: Practically limit "Dummy wait" workaround to old Intel systems

BugLink: https://bugs.launchpad.net/bugs/1990985

Old, circa 2002 chipsets have a bug: they don't go idle when they are
supposed to. So, a workaround was added to slow the CPU down and
ensure that the CPU waits a bit for the chipset to actually go idle.
This workaround is ancient and has been in place in some form since
the original kernel ACPI implementation.

But, this workaround is very painful on modern systems. The "inl()"
can take thousands of cycles (see Link: for some more detailed
numbers and some fun kernel archaeology).

First and foremost, modern systems should not be using this code.
Typical Intel systems have not used it in over a decade because it is
horribly inferior to MWAIT-based idle.

Despite this, people do seem to be tripping over this workaround on
AMD system today.

Limit the "dummy wait" workaround to Intel systems. Keep Modern AMD
systems from tripping over the workaround. Remotely modern Intel
systems use intel_idle instead of this code and will, in practice,
remain unaffected by the dummy wait.

Reported-by: K Prateek Nayak <kprateek.nayak@amd.com>
Suggested-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Tested-by: K Prateek Nayak <kprateek.nayak@amd.com>
Link: https://lore.kernel.org/all/20220921063638.2489-1-kprateek.nayak@amd.com/
Link: https://lkml.kernel.org/r/20220922184745.3252932-1-dave.hansen@intel.com
(cherry picked from commit e400ad8b7e6a1b9102123c6240289a811501f7d9)
Signed-off-by: Jeff Lane <jeffrey.lane@canonical.com>

Author: Joerg Roedel
Author Date: 2019-04-12 10:50:31 UTC

iommu/amd: Set exclusion range correctly

BugLink: https://bugs.launchpad.net/bugs/1823037

The exlcusion range limit register needs to contain the
base-address of the last page that is part of the range, as
bits 0-11 of this register are treated as 0xfff by the
hardware for comparisons.

So correctly set the exclusion range in the hardware to the
last page which is _in_ the range.

Fixes: b2026aa2dce44 ('x86, AMD IOMMU: add functions for programming IOMMU MMIO space')
Signed-off-by: Joerg Roedel <jroedel@suse.de>
(cherry picked from commit 3c677d206210f53a4be972211066c0f1cd47fe12 5.2-rc1)
Signed-off-by: Jeffrey Lane <jeffrey.lane@canonical.com>